Flip-flop devices are one of the fundamental building blocks of digital integrated circuits and systems. Typical high performance flip-flop devices include sense amplifier flip-flops (SAFF), hybrid latch flip-flops (HLFF) and semi-dynamic flip-flops (SDFF). One conventional sense amplifier flip-flop is described in an article by B. Nikolic et al. entitled “Sense Amplifier-Based Flip Flop,” IEEE International Solid-State Circuits Conference, ISSCC99, Paper TP 16.5, pp. 282-283 and 468 (1999). As illustrated by FIG. 16.5.2 of the Nikolic et al. article, the SAFF integrates logic into the flip-flop in order to generate output signals Q and /Q having equal rising and falling transitions. This SAFF is more fully illustrated by U.S. Pat. Nos. 6,633,188 B1 and 6,107,853. U.S. Pat. No. 6,396,309 B1 to Zhao et al. discloses a clocked SAFF that utilizes a keeper unit to prevent the occurrence of a floating data node. U.S. Patent Application No. 2002/0140480 A1 to Lu et al. discloses a clocked SAFF having an input circuit, a sense amplifier and an output circuit that purportedly reduce setup time.
FIG. 1 illustrates a conventional sense amplifier flip-flop 10 that uses a series of inverters of increasing size to buffer an output signal that is generated by logic. These inverters are illustrated by the labels x, 3x and 9x to represent a factor of three scaling. As illustrated, the sense amplifier stage 12 of the flip-flop 10 is responsive to a pair of complementary data signals D and DB and a clock signal CLK. When the clock signal CLK is set to an inactive level (i.e., CLK=0), the outputs SETB (=/SET) and RESETB (=/RESET) of the sense amplifier stage 12 are driven to (or held at) logic 1 levels and the output Q of the flip-flop 10 retains its previously set state. The logic that evaluates the values of the outputs SETB and RESETB includes a pair of cross-coupled NAND gates. When the true data input D equals 1 (DB=0) and a rising edge of the clock signal CLK is received, the output SETB is switched high-to-low to trigger a leading edge of a logic 0 pulse and the output RESETB remains high. This switching event causes the output Q of the flip-flop 10 to be switched high from a previously low state (or held high if previously set high), in response to a rising edge of the clock signal CLK. In contrast, when the data input D equals 0 (DB=1) and a rising edge of the clock signal CLK is received, the output RESETB is switched high-to-low to trigger a leading edge of a logic 0 pulse and the output SETB remains high. This switching event causes the output Q of the flip-flop 10 to be switched low from a previously high state (or held low if previously set low), in response to a rising edge of the clock signal CLK.
Unfortunately, the flip-flop 10 of FIG. 1 fails to fully exploit the pulsed nature of the signals generated at the outputs of the sense amplifier 12 to thereby minimize the CLK-to-Q timing when driving the output Q high (when D=1 and a rising edge of the clock signal CLK is received) or driving the output Q low (when D=0 and a rising edge of the clock signal CLK is received). Instead, the plurality of scaled inverters at the output of the flip-flop 10 are designed to support both high-to-low and low-to-high transitions having substantially equal pull-up and pull-down slew rates. Thus, notwithstanding the sense amplifier flip-flop 10 of FIG. 1, there continues to be a need for flip-flops having better CLK-to-Q timing characteristics.